法国专利FR3048306A1 SUPPORT FOR A SEMICONDUCTOR STRUCTURE

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专利摘要:
The invention relates to a carrier (1) for a semiconductor structure comprising a charge trapping layer (2) on a base substrate (3). The trapping layer (2) consists of a polycrystalline main layer (2a) and, interposed in the main layer (2a) or between the main layer (2a) and the base substrate (3), of at least one polycrystalline interlayer (2b) composed of an alloy of silicon and carbon or carbon, the interlayer (2b) having a resistivity greater than 1000 ohm. cm
公开号:FR3048306A1
申请号:FR1651642
申请日:2016-02-26
公开日:2017-09-01
发明作者:Christophe Figuet；Oleg Kononchuk；Kassam Alassaad；Gabriel Ferro；Veronique Souliere
申请人:Universite Claude Bernard Lyon 1 UCBL；Soitec SA；
IPC主号:

专利说明:

SUPPORT FOR A SEMICONDUCTOR STRUCTURE FIELD OF THE INVENTION
The present invention relates to a support for a semiconductor structure.
BACKGROUND OF THE INVENTION
Integrated devices are usually formed on substrates which serve mainly to support their manufacture. However, the increase in the degree of integration and the expected performance of these devices leads to an increasingly important coupling between their performance and the characteristics of the substrate on which they are formed. This is particularly the case for RF devices, processing signals whose frequency is between about 3kHz and 300GHz, which find particular application in the field of telecommunications (telephony, Wi-Fi, Bluetooth ...). As an example of device / substrate coupling, the electromagnetic fields, originating from the high frequency signals propagating in the integrated devices, penetrate into the depth of the substrate and interact with the possible charge carriers therein. It follows a useless consumption of a part of the signal energy by loss of coupling and possible influences between components by crosstalk ("crosstalk" according to the English terminology).
According to a second example of coupling, the charge carriers of the substrate can cause the generation of unwanted harmonics, which can interfere with the signals propagating in the integrated devices and degrading their qualities.
These phenomena are particularly observable when the substrate used comprises a buried layer of insulation between a support and a useful layer on and in which the integrated devices are formed. The charges trapped in the insulation lead to accumulate under this layer of insulation, in the support, charges of complementary signs forming a conductive plane. In this conductive plane, the mobile charges are likely to interact strongly with the electromagnetic fields generated by the components of the useful layer.
To protect or limit this phenomenon, it is known to insert between the buried insulator and the support, directly under the insulator, a charge trapping layer, for example a layer of 1 to 5 microns of polycrystalline silicon. The grain boundaries forming the poly-crystal then constitute traps for the charge carriers, which can come from the trapping layer itself or the underlying support. In this way, it prevents the appearance of the conductive plane under the insulation.
The device / substrate coupling then depends on the intensity of interaction of the electromagnetic fields with the mobile charges of the support. The density and / or mobility of these charges are a function of the resistivity of the support.
When the resistivity of the substrate is relatively high (and therefore a relatively low charge density), greater than 1000 ohm.cm, a trapping layer of 1 to 5 microns thick can be adapted to limit the device / substrate coupling. This preserves the integrity of the signals, and thus the radiofrequency performance of the integrated devices of the useful layer.
When, on the contrary, the resistivity of the substrate is lower, less than 1000 ohm.com, or when the expected performance of the integrated device is high, it would be desirable to be able to form a very thick trapping layer, greater than 5 microns, even at 10 or 15 microns, to push the area in which the charges are mobile more deeply into the substrate. Interactions with electromagnetic fields propagating very deeply could be prevented, and the performance of the integrated devices of the useful layer could be further improved.
However, it has been observed that a trapping layer thickness greater than 5 microns does not lead to the expected performance improvement.
The document US 20150115480 discloses a substrate comprising a support for a semiconductor structure, the support being provided with a trapping layer formed of a stack of polycrystalline or amorphous layers of silicon, silicon germanium, silicon carbide and / or or germanium. These layers are passivated, that is to say that their interfaces consist of a thin layer of insulator such as an oxide of silicon or silicon nitride. Such passivation is obtained, according to this document, by exposing the free surface of these layers during their manufacture, to an environment rich in oxygen or nitrogen.
According to this document, the multilayer structure of the trapping layer would prevent the phenomenon of recrystallization of the polycrystalline trapping layer when the substrate is exposed to a very high temperature, for example during its manufacture or the manufacture of integrated devices on this substrate. When the trapping layer recrystallizes, even partially, the RF performance of the substrate and the integrated devices that will be formed therefrom are affected, which is of course not desirable.
The support proposed by this document is not entirely satisfactory.
Firstly, the thin layers of passivation insulator that this document plans to form are generally not stable in temperature, especially when this insulator is silicon dioxide. High temperature exposure of the support can lead to the dissolution of the oxide in the polycrystalline layers, and the disappearance of the passivation layers. The trapping layers are then likely to recrystallize if the high temperature treatment of the support continues.
If these insulating passivation layers are formed with sufficient thickness to ensure their temperature stability, they then form barriers to the diffusion of charges present in the support and in the layers of the stack. When the traps of one layer of the stack are all saturated in charge carriers, these remain confined in the layer and accumulate there, and can not be dragged to other traps available in other layers of stacking. The RF performance of the substrate is therefore deteriorated.
In addition, the charges trapped in the relatively thick insulating passivation layers lead to forming conductive planes beneath their surface, reproducing the phenomena observed under a buried oxide layer of a SOI structure which have been described previously. The polycrystalline structure of the trapping layers can only partially compensate for this amount of additional charges. Again, the RF performance of the substrate is deteriorated.
OBJECT OF 1 / INVENTION
The present invention aims to overcome all or part of the aforementioned drawbacks.
BRIEF DESCRIPTION OF THE INVENTION
In order to achieve one of these objects, the object of the invention provides a support for a semiconductor structure comprising a charge trapping layer disposed on a base substrate. According to the invention, the trapping layer consists of a polycrystalline main layer and, interposed in the main layer or between the main layer and the base substrate, at least one polycrystalline intermediate layer composed of a silicon alloy and carbon or carbon, the interlayer having a resistivity greater than 1000 ohm.cm.
The trapping layer is in this way stable in temperature, without the disadvantages of the insulating passivation layers of the state of the art.
According to other advantageous and nonlimiting features of the invention, taken alone or in any technically feasible combination: • the base substrate has a resistivity greater than 1000 ohm.cm; • the trapping layer has a thickness greater than 10 microns; • The support comprises between 1 and 10 interlayers; The polycrystalline main layer consists of silicon grains with a size of between 100 nm and 1000 nm; Each interlayer has a thickness of less than 10 nm or 5 nm; • The support includes a layer of insulation on the charge trapping layer; The polycrystalline interlayer (s) is composed of an alloy of silicon and carbon having more than 5% of carbon, such as silicon carbide. The object of the invention also relates to a semiconductor structure comprising such a support, an insulating layer on the support and a useful layer on the insulating layer. The useful layer may contain at least one component. The object of the invention finally relates to a method of manufacturing a semiconductor structure comprising the following steps: a. provide a support as previously described; b. forming on this support, the semiconductor structure. The formation step b may comprise the transfer of a useful layer on the support.
The useful layer may comprise at least one integrated device.
BRIEF DESCRIPTION OF THE DRAWINGS Other characteristics and advantages of the invention will emerge from the detailed description of the invention which will follow with reference to the appended figures in which:
Figure 1 shows schematically a support for a semiconductor structure according to the invention; FIG. 2 represents the relationship existing between the thickness of a polycrystalline layer and the average grain size at the surface of this layer; FIG. 3 represents a substrate of the semiconductor-on-insulator type comprising a support according to the invention.
DETAILED DESCRIPTION OF THE INVENTION
Figure 1 shows schematically a support for a semiconductor structure according to the invention. The support 1 may have the shape of a plate, circular, of standardized size, for example 200 mm or 300 mm, or 450 mm in diameter. But the invention is not limited to its size or shape.
Thus, in the case where the semiconductor structure is a finished or semi-finished integrated device, the support 1 will take the form of a block of rectangular or square longitudinal section material whose dimensions, from a few millimeters to a few centimeters, correspond to the dimensions of the integrated device.
The support 1 comprises a base substrate 3, typically several hundred microns thick. Preferably, and especially when the support 1 is intended to receive a semiconductor structure whose expected RF performance is high, the base substrate has a high resistivity greater than 1000 ohm.centimeter, and more preferably still greater than 3000 ohm. centimeter. This limits the density of charges, holes or electrons, which are likely to move in the base substrate. But the invention is not limited to a base substrate having such a resistivity, and it also provides RF performance advantages when the base substrate has a more consistent resistivity of the order of a few hundred ohm. centimeters.
For reasons of availability and cost, the base substrate is preferably made of silicon. It may be for example a substrate CZ low interstitial oxygen which has, as is well known per se, a resistivity which may be greater than 1000 ohm. centimeter. The base substrate may alternatively be formed of another material: it may be for example sapphire, silicon carbide, ....
The support 1 also comprises, directly in contact with the base substrate 3, a trapping layer 2. As has been mentioned in detail in the introduction to the present application, the trapping layer has the function of trapping the charge carriers may be present in the support 1 and limit their mobility. This is particularly the case when the support 1 is provided with a semiconductor structure emitting an electromagnetic field penetrating the support is therefore likely to interact with these charges.
According to the invention, the trapping layer 2 comprises a polycrystalline main layer 2a.
For the same reasons of availability and cost that have already been mentioned, the main layer 2a is preferably made of polycrystalline silicon. But it may consist of another semiconductor and polycrystalline material, or comprise a part (for example a section 2a of the layer 2 in Figure 1) of another semiconductor material and polycrystalline. It may be for example germanium, silicon germanium, ....
In all cases, the main layer 2a has a high resistivity greater than 3000 ohm.centimeter. For this purpose, the main layer 2a is not intentionally doped, that is, it has a dopant concentration of less than 10 14 atoms per cubic centimeter. It can be rich in nitrogen or carbon to improve its resistivity characteristic.
The trapping layer 2 also comprises, interposed in the main layer 2a or between the main layer 2a and the base substrate 3, at least one polycrystalline intermediate layer composed of a silicon and carbon or carbon alloy, having a resistivity greater than 1000 ohm.centimeter. These materials are very stable in temperature, that is to say that even exposed to very high temperatures exceeding those which are generally used for the manufacture of semiconductor structures (500 ° to 1300 °), these materials preserve their micro and macroscopic structure.
By intercalating at least one such interlayer 2b in the polycrystalline main layer 2a, a stable temperature stack is formed which prevents the recrystallization of the polycrystalline main layer 2a during the heat treatments that the support 1 can undergo. As regards resistive semiconductor materials, the drawbacks associated with the use of an insulating material are overcome. In addition, their resistivity and polycrystallinity properties contribute to the trapping of charges in layer 2, similar to what occurs in the main layer 2a.
When the support 1 comprises several intermediate layers 2b, these may be of the same nature or of a different nature, this nature remaining chosen from the list of the aforementioned materials.
The trapping layer 2 formed, on a base substrate, of the main layer 2a and at least one intermediate layer 2b, thus forms a support for a semiconductor structure stable in temperature, that is to say little subject to recrystallization, and effective for trapping charge carriers. It has a very high density of traps accessible to loads.
Moreover, by intercalating at least one layer 2b in the main layer 2a, it was surprisingly observed that it was possible to form a trapping layer 2 with a thickness greater than 2 microns, allowing improve the RF performance of the support.
This property is illustrated with reference to FIG. 2, the description of which follows. On standard CZ silicon substrates, polycrystalline silicon layers have been formed according to the state of the art and of increasing thickness. For each of these layers, and on their surfaces, the average size of the grains of the polycrystal was found by SEM imaging (acronym for the expression "Surface Electron Microscopy", scanning electron microscopy).
The graph of FIG. 2 represents (in the form of a black square) the relationship existing between the thickness of a polycrystalline layer (in abscissa and in microns) and the average size of the grains at the surface of this layer (in ordinate and in nanometers). It is observed that the thicker the layer, the larger the grains.
A thick trapping layer may be desired to push the residual area of charge carriers further down the support. However, this leads, as we observe, to an increase in the size of the grains on the surface of the trapping layer. This surface is intended to be placed just below the semiconductor structure, it is therefore likely to be subjected to a large magnetic field. The RF performance of the semiconductor structure will therefore be very sensitive to the behavior of the charge carriers at this surface and its proximity.
However, an increase in grain size is problematic in two ways. First, larger grains result in lower grain density. These joints forming a preferred area for trapping carriers, the density of traps is reduced. On the other hand, the grains also form a confinement space for the charge carriers that reside there. In grains of large size, for example of the order of magnitude of an integrated device, the charges behave, seen from the device, as in a material without defects.
These two aspects combine to reduce the RF performance of the support, when the polycrystalline grains of the trapping layer are of large sizes.
Additional studies have shown that the grain size should preferably be between 100 nm (below which their thermal stability is no longer assured and where there is a risk of their recrystallization temperature) and 1000 nm (beyond which the RF performance of the medium is affected). This characteristic of grains could never be obtained for a thickness of the trapping layer greater than about 5 microns, and over all your thickness.
On a base substrate identical to that of the previous example, an intermediate layer of polycrystalline silicon of about eight microns was formed. At mid-thickness of this layer, a layer of silicon carbide of lnm was formed. The surface grain size of the polycrystalline silicon layer was measured on the order of 800 nm.
On a second base substrate, a polycrystalline silicon layer of about 13 microns was formed. Five layers of 80 nm silicon carbide were intermittently inserted into the polycrystalline layer. The size of the grains on the surface of this layer has been measured on the order of 800 nm.
On a third base substrate, a polycrystalline silicon layer of about 13 microns was formed. Eleven layers of 40 nm thick silicon carbides have been intercalated regularly in the polycrystalline layer. The surface grain size of this layer was measured on the order of 125 nm.
The three measurements were placed on the graph of FIG. 2 and respectively labeled A, B, C on this graph.
It is very apparent in this figure that the insertion of the intermediate layers makes it possible to control the evolution of the size of the grains in the thickness of the trapping layer, and that it is possible to obtain grains of sizes between 100 and 1000 nanometers, even for layer thicknesses greater than 5 or 10 microns.
According to a (nonlimiting) assumption of interpretation of these results, the intermediate layer (or layers) composed of a silicon and carbon alloy has a significant mesh parameter difference with the polycrystalline silicon of the main layer (the parameter mesh size of the interlayer being smaller than that of the main layer). In this way, a very large density of crystalline defects is generated, and the epitaxial relationship between the polysilicon layers and the interlayer is lost during their growth. The particular polycrystalline arrangement of the main layer under an interlayer is lost, and is not reproduced in the portion of the main layer above the interlayer.
These observations make it possible to establish advantageous characteristics of the trapping layer 2 according to the invention.
Thus the trapping layer may advantageously comprise between 1 and 10 interlayers. In this way, and without forming an excessively complex and expensive stack, it is possible to control the size of the grains of the trapping layer 2 a, even for thicknesses of trapping layers 2 which are large, greater than 5 microns, and even greater than 10. microns.
Preferably, each intermediate layer 2b formed of an alloy of silicon and carbon or formed of carbon, has a mesh parameter less than the mesh parameter of the material (or materials) forming the main layer 2a.
Advantageously, the thickness of the main layer portion 2a between two successive intercalated layers 2b may be between 0.2 and 2.5 micron. This prevents the grains become too large in the upper portion of this portion.
The trapping layer 2 may have a thickness greater than 2, or even 10 microns. Whether its thickness is greater or less than these limits, the main layer 2a may be composed of grain whose size is between 100 and 1000 nanometers. We then obtain a support 1 having RF performance greatly improved compared to what is possible to obtain with the supports according to the state of the art.
An alloy of silicon and carbon, or carbon, forming the interlayer (s), may have a coefficient of thermal expansion very different from that forming the main layer 2a. In this case, it is preferable to limit their thickness, for example less than 10 or 5 nm. This avoids creating stress in the support 1 when it is subjected to a high temperature. The silicon and carbon alloy may be silicon carbide, or carbon-doped silicon. Preferably, the carbon-doped silicon has more than 5% of carbon.
Finally, and as shown in FIG. 1, the support can have an insulating layer 4 directly on the trapping layer 2. This optional insulating layer 4 can facilitate the assembly of the support 1 with a structure semiconductor.
The manufacture of the support 1 according to the invention is particularly simple and feasible with standard deposit equipment industry.
In one example, base substrate 3 is provided and placed in a conventional deposition chamber. As is well known per se, the base substrate 3 may be prepared prior to deposition, for example to remove a native oxide layer from its surface. This step is not mandatory and this oxide can be preserved. It is indeed sufficiently fine, from 1 to 2 nm, not to have an insulating effect (conduction through this layer by tunnel effect) insofar as future thermal treatments will not have made it completely disappear by dissolution .
The chamber is traversed by a flow of precursor gases, for example SiH 4, at a temperature of about 1000 ° C to grow the main layer 2a, in this case polycrystalline silicon.
At given instants of this deposition process, a second precursor gas, for example C3H8, may be introduced into the chamber for a predetermined period of time in order to form the intermediate layer (s) 2b.
The flow of the first gas may be interrupted during this time interval, so as to form a spacer layer 2b rich, or consisting of carbon.
Alternatively, the flow of the first gas can be maintained during this time interval, so as to form an interlayer 2b consisting of an alloy of silicon and carbon. The proportion of carbon and silicon in this alloy can be controlled by adjusting the respective precursor streams.
This sequence can be repeated to form the targeted trapping layer 2, the circulation time of the different flows determining the thickness separating the successive layers 2a, 2b.
At the end of this deposition phase, a support 1 according to the invention is available. This may undergo an optional polishing step on the side of the trapping layer 2, to provide a smooth surface facilitating its assembly with a semiconductor structure.
The support may be provided with a layer of insulation 4, for example a silicon oxide or a silicon nitride, deposited in a conventional manner. This insulator 4 can also be polished.
As already mentioned, the support 1 is intended to receive a semiconductor structure on the side of the trapping layer 2.
This structure can be formed in many ways on the support 1, but advantageously this formation comprises a step of transferring a useful layer 5 to the support.
As is well known in itself, this transfer is usually carried out by assembling the face of a donor substrate to the support 1. This may be provided with the insulating layer 4 or not. In the same way, the donor substrate may have been previously provided with an insulating layer 6 of the same nature or of a different nature from the insulating layer 4. It may be, for example, silicon oxide or nitride oxide. silicon.
After this assembly step, the donor substrate is reduced in thickness to form the useful layer 5. This reduction step can be performed by mechanical or chemical thinning. It may also be a fracture in a fragile zone previously introduced into the donor substrate, for example according to the principles of Smart Cut ™ technology.
Finishing steps of the useful layer 5, such as a polishing step, a heat treatment under a reducing or neutral atmosphere, a sacrificial oxidation can be chained to the thickness reduction step.
When the donor substrate is a simple substrate, that is to say it does not comprise an integrated device, a semiconductor-on-insulator-type substrate is formed, in which the useful layer is a semiconductor layer. virgin drivers, comprising the support of the invention and as shown in FIG. 3. The substrate can then be used for the formation of integrated devices.
When the donor substrate has been previously treated to form integrated devices on its surface, a useful layer 5 comprising these devices is available at the end of this process.
Semiconductor structure denotes indifferently an integrated device that it is formed based on semiconductor materials or not. For example, it may be a surface acoustic wave or volume type device, typically made on and in a layer of piezoelectric material, such as lithium tantalate.
Semiconductor structure also denotes a blank layer of device material, based on semiconductor material or not, and in which integrated devices may be formed.

权利要求:
Claims (14)
[1" id="c-fr-0001]
1. Support (1) for a semiconductor structure comprising a charge trapping layer (2) disposed on a base substrate (3) characterized in that the trapping layer (2) consists of a polycrystalline main layer (2a) and, interposed in the main layer (2a) or between the main layer (2a) and the base substrate (3), at least one intercalary layer (2b) polycrystalline composed of a silicon alloy and carbon or carbon, the interlayer (2b) having a resistivity greater than 1000 ohm.cm.
[2" id="c-fr-0002]
2. Support (1) according to the preceding claim wherein the base substrate (3) has a resistivity greater than 1000 ohm.cm.
[3" id="c-fr-0003]
3. Support (1) according to one of the preceding claims wherein the trapping layer (2) has a thickness greater than 5 or 10 microns.
[4" id="c-fr-0004]
4. Support (1) according to one of the preceding claims comprising between 1 and 10 interlayers (2b).
[5" id="c-fr-0005]
5. Support (1) according to one of the preceding claims wherein the polycrystalline main layer (2a) consists of silicon grains of size between 100 nm and 1000 nm.
[6" id="c-fr-0006]
6. Support (1) according to one of the preceding claims wherein each intermediate layer (2b) has a thickness less than 10 nm or 5 nm.
[7" id="c-fr-0007]
7. Support (1) according to one of the preceding claims, comprising an insulating layer (4) on the charge trapping layer (2).
[8" id="c-fr-0008]
8. Support (1) according to one of the preceding claims, wherein the polycrystalline interlayer (s) (2b) is composed of an alloy of silicon and carbon having more than 5% carbon.
[9" id="c-fr-0009]
9. Support (1) according to the preceding claim wherein the intermediate layer (2b) is silicon carbide.
[10" id="c-fr-0010]
10. Semiconductor structure comprising: - a support according to one of claims 1 to 9; - a layer of insulation (4, 6) on the support; a useful layer (5) on the insulating layer.
[11" id="c-fr-0011]
11. Semiconductor structure according to the preceding claim wherein the useful layer (5) comprises at least one integrated device.
[12" id="c-fr-0012]
12. A method of manufacturing a semiconductor structure comprising the following steps: a. providing a support (1) according to one of claims 1 to 9; b. forming, on the support (1), the semiconductor structure.
[13" id="c-fr-0013]
13. Method according to the preceding claim wherein the forming step b comprises the transfer of a useful layer (5) on the support.
[14" id="c-fr-0014]
14. Method according to the preceding claim wherein the useful layer (5) comprises at least one integrated device.

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引用文献:

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US10468486B2|2017-10-30|2019-11-05|Taiwan Semiconductor Manufacturing Company Ltd.|SOI substrate, semiconductor device and method for manufacturing the same|CN108884593B|2016-04-05|2021-03-12|株式会社希克斯|Polycrystalline SiC substrate and method for producing same|

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JP2021190660A|2020-06-04|2021-12-13|株式会社Sumco|Support substrate for bonded wafers|

CN111979524B|2020-08-19|2021-12-14|福建省晋华集成电路有限公司|Polycrystalline silicon layer forming method, polycrystalline silicon layer and semiconductor structure|

法律状态:
2017-01-23| PLFP| Fee payment|Year of fee payment: 2 |

2017-09-01| PLSC| Publication of the preliminary search report|Effective date: 20170901 |

2018-01-23| PLFP| Fee payment|Year of fee payment: 3 |

2018-02-09| TQ| Partial transmission of property|Owner name: UNIVERSITE CLAUDE BERNARD LYON 1, FR Effective date: 20180108 Owner name: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, FR Effective date: 20180108 Owner name: SOITEC, FR Effective date: 20180108 |

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2021-01-26| PLFP| Fee payment|Year of fee payment: 6 |

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优先权:

申请号 | 申请日 | 专利标题

FR1651642A|FR3048306B1|2016-02-26|2016-02-26|SUPPORT FOR A SEMICONDUCTOR STRUCTURE|

FR1651642|2016-02-26|FR1651642A| FR3048306B1|2016-02-26|2016-02-26|SUPPORT FOR A SEMICONDUCTOR STRUCTURE|

KR1020187025017A| KR20190013696A|2016-02-26|2017-02-23|Support for semiconductor structure|

CN201780013336.3A| CN109155276A|2016-02-26|2017-02-23|Supporting element for semiconductor structure|

JP2018544865A| JP6981629B2|2016-02-26|2017-02-23|Support for semiconductor structure|

PCT/FR2017/050400| WO2017144821A1|2016-02-26|2017-02-23|Carrier for a semiconductor structure|

US16/080,279| US11251265B2|2016-02-26|2017-02-23|Carrier for a semiconductor structure|

EP17710350.4A| EP3420583B1|2016-02-26|2017-02-23|Carrier for a semiconductor structure|

TW106106332A| TW201742108A|2016-02-26|2017-02-24|Support for a semiconductor structure|

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